1. Field of the Invention
This invention relates to one-shot logic circuits, and more particularly, to emitter coupled logic (ECL) one-shots.
2. Description of the Prior Art
Previously a high speed ECL one-shot has not been available on the market. Some transistor transistor logic (TTL) one-shot circuits have been available but the flexibility and features which they provided had been limited. The requirement for a versatile high speed ECL one-shot which was compatible with other ECL logic circuits has not been met by prior art circuits.
Prior art one-shots typically use RC timing circuits. Upon receiving a trigger pulse, these one-shot circuits pass through two cycles--a discharge cycle which initializes the charge on the timing capacitor via a relatively small internal resistance (typically 1.5k) and a timing cycle which charges the timing capacitor through a large external timing resistor to a threshold level which, when attained, terminates the timing pulse.
Circuits of this variety have not been able to offer a full retrigger capability because trigger pulses received during the discharge cycle are ignored. For short timing intervals, the discharge cycle is a significant portion of the timing cycle (up to 50%). Therefore, a considerable retrigger dead zone exists.
This circuit of the present invention accepts a trigger pulse at any time by storing the trigger pulses occurring during the timing interval as retrigger pulses on a separate retrigger flip-flop thereby giving the circuit a full retrigger capability.
This same inability to quickly restore the charge on the timing capacitor prevented prior art one-shots from being immediately able to receive a subsequent input signal after a reset signal had been received. Prior art one-shot circuits typically were not able to receive an additional input signal until the RC timing circuit had been timed out in a normal manner.
Therefore, it is a feature of this invention to provide a versatile, high speed ECL one-shot circuit which is fully retriggerable such that any continuous input pulse train faster than the output pulse width will cause the one-shot output pulse to continue until one pulse width after the last input pulse.
It is another feature of this invention to provide a high speed, versatile ECL one-shot which is resettable such that the reset input terminates the output pulse and immediately restores the timing capacitor charged to initial conditions.
It is yet another feature of the present invention to provide a versatile, high speed ECL one-shot providing logic input trigger controllability which determines whether the one-shot triggers on positive edges, negative edges, both, or neither.
It is still another feature of this invention to provide a versatile, high speed ECL one-shot with current controllability such that an external current can control the output pulse width.
It is yet another feature of this invention to provide a versatile, high speed ECl one-shot having an input buffered by Schmidt triggers to enhance the timing accuracy for inputs having slow rise and fall times.
It is still another feature of this invention to provide a versatile, high speed ECL one-shot having a high speed input which bipasses the input Schmidt triggers for minimum input to output delay operation.